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Programmable Logic Design Engineer

Entreprise
ViaSat Antenna Systems SA
Lieu
Lausanne
Date
21.05.2026
Référence
298019

Role Overview

This position entails the development of advanced FPGA designs for next-generation terminal products, with a focus on interfaces, high-speed signal processing algorithms, and network protocols. The individual will oversee the entire design process, from requirements gathering to documentation and integration, ensuring comprehensive execution at each stage.

Responsibilities

  • Collaborate with team members to develop high-speed digital signal processing and waveform processing algorithms for satellite communications applications.
  • Create testbenches and assist in maintaining the system-level verification environment.
  • Synthesize Verilog and System Verilog for Altera and Xilinx/AMD FPGAs.
  • Develop timing constraints, analyze timing results, and execute design modifications necessary to meet timing requirements.
  • Generate and collaborate on essential design documents, development requirements, specifications, and verification protocols.
  • Take ownership of technical challenges and drive them to resolution.
  • Integrate and debug designs in a laboratory setting.

Qualifications

  • Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field.
  • 10-12 years of FPGA design experience, particularly with Altera Quartus and Xilinx Vivado.
  • Strong knowledge of System Verilog.
  • Experience with RTL design for various signal processing blocks, including equalizers, correlators, filters, and FEC encoders and decoders.
  • A proven track record in designing and implementing FPGA modules using System Verilog, including simulation and testbench development.
  • Ability to work independently, demonstrate initiative, and take ownership of projects and deliverables.
  • Strong written and verbal communication skills, with the capability to collaborate within a geographically distributed team.

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